1. Field of the Invention
The present invention refers to a memory device and to memory device parts for transmitting and receiving signals in a synchronous way.
2. Description of the Related Art
A conventional memory device comprises an array of memory cells, a control logic for addressing single memory cells or groups of memory cells and for writing data to and reading data from the array of memory cells and an input/output section. The memory device exchanges data, address and control signals via the input/output section with circuits external to the memory device, for example, with a memory controller. The array of memory cells, a control logic and the input/output section include interfaces for communication between them. Signal exchange between the interfaces of the array of memory cells, the control logic and the input/output section is asynchronous.
The input/output section comprises receiver circuits and on-chip drivers (OCD) serving as interface for communication with the circuits external to the memory device. The input/output section is subdivided into a first part for receiving control signals from the external circuits and a second part for receiving address and data signal from and transmitting data signals to the external circuits.
In future computers, the rate of data exchange between the processor, the memory controller and the memory devices will further grow. Therefore, the memory devices will transmit and receive data, address and control signals via high speed interfaces with very high bit rates on each single line.
On the other hand, due to the constraints of the semiconductor technology used for the production of memory devices, the bit rates on internal lines of memory devices will be much lower and rise much slower than the external bit rates. Therefore, the input/output section will convert external bit rates to internal bit rates and internal bit rates to external bit rates by a high and still rising factor. To keep the total amount of data constant, the number of parallel internal lines and the number of parallel external lines differs by the same factor. If, for example, the external bit rate is four times as high as the internal bit rate, the number of parallel internal lines will be four times as many as the number of external lines.
The conversion of lowly parallel (i.e., relatively few parallel lines; e.g., eight or less parallel lines) high bit rate external data transfer to highly parallel (i.e., relatively high number of parallel lines; e.g., sixty four or more parallel lines) low bit rate internal data transfer and vice versa in the inpuVoutput section is highly error-prone. The risk of an error increases with the factor of conversion.